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</style><table class="infobox"><caption class="infobox-title">Intel Pentium II</caption><tbody><tr><td colspan="2" class="infobox-image"><div class="infobox-caption">Original Pentium II MMX case badge</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">May 7, 1997<span style="display:none"> (<span class="bday dtstart published updated">1997-05-07</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">December 26, 2003<span style="display: none;"> (<span class="dtend">2003-12-26</span>)</span> (all, including embedded units)<sup id="cite_ref-embdiscontinued_1-0" class="reference"><a href="#cite_note-embdiscontinued-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><br>January 1, 2005<span style="display: none;"> (<span class="dtend">2005-01-01</span>)</span> (discontinuation and end of life)</td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">

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</style><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">Klamath: 80522<br>Deschutes and Tonga: 80523<br>Dixon: 80524</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">233 MHz to 450 MHz</td></tr><tr><th scope="row" class="infobox-label"><a href="Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">66 MT/s to 100 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">32 KB (16 KB data + 16 KB instructions)</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256–512 KB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">350 nm to 180 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="IA-32" title="IA-32">IA-32</a></td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="Physical_Address_Extension" title="Physical Address Extension">PAE</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Transistor_count" title="Transistor count">Transistors</a></th><td class="infobox-data"><div class="plainlist"><ul><li><b>Klamath</b>: 7.5 million</li><li><b>Deschutes</b>: 7.5 million</li><li><b>Tonga</b>: 7.5 million</li><li><b>Dixon</b>: 27.4 million</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>1</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Sockets</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="Slot_1" title="Slot 1">Slot 1</a></li><li><a href="MMC-1" title="MMC-1">MMC-1</a></li><li><a href="MMC-2" title="MMC-2">MMC-2</a></li><li><a href="Mini-Cartridge" title="Mini-Cartridge">Mini-Cartridge</a></li><li>PPGA-B615 (<a href="Micro-PGA1" class="mw-redirect" title="Micro-PGA1">μPGA1</a>)</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Core names</th><td class="infobox-data"><div class="plainlist"><ul><li>Klamath (desktop)</li><li>Deschutes (desktop)</li><li>Tonga (mobile)</li><li>Dixon (mobile)</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessors</th><td class="infobox-data"><a href="Pentium_(original)" title="Pentium (original)">Pentium</a>, <a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, <a href="Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a></td></tr><tr><th scope="row" class="infobox-label">Successors</th><td class="infobox-data"><a href="Pentium_III" title="Pentium III">Pentium III</a> (SSE successor), <a href="Celeron" title="Celeron">Celeron</a>, <a href="Pentium_4" title="Pentium 4">Pentium 4</a> (SSE2 successor)</td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Unsupported</td></tr></tbody></table>

<p>The <b>Pentium II</b><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> is a brand of sixth-generation <a href="Intel" title="Intel">Intel</a> <a href="X86" title="X86">x86</a> <a href="Microprocessor" title="Microprocessor">microprocessors</a> based on the <a href="P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <a href="Microarchitecture" title="Microarchitecture">microarchitecture</a>, introduced on May 7, 1997. It combined the <i>P6</i> microarchitecture seen on the <a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a> with the <a href="MMX_(instruction_set)" title="MMX (instruction set)">MMX instruction set</a> of the <a href="Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a>, and is the second processor using the <a href="Pentium_(brand)" class="mw-redirect" title="Pentium (brand)">Pentium</a> brand.

</p><p>Containing 7.5 million <a href="Transistor" title="Transistor">transistors</a> (27.4 million in the case of the mobile Dixon with 256 <a href="Kilobyte" title="Kilobyte">KB</a> on-die <a href="CPU_Cache" class="mw-redirect" title="CPU Cache">L2 cache</a>), the Pentium II featured an improved version of the first <i>P6</i>-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pro's. In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based <a href="Celeron" title="Celeron">Celeron</a> line of processors for low-end computers and the Intel <a href="Pentium_II_Xeon" class="mw-redirect" title="Pentium II Xeon">Pentium II Xeon</a> line for servers and workstations. The Celeron was characterized by a reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was characterized by a range of full-speed L2 cache (from 512 KB to 2048 KB), a 100 MT/s FSB, a different physical interface (<a href="Slot_2" title="Slot 2">Slot 2</a>), and support for <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a>.

</p><p>In February 1999, the Pentium II was replaced by the nearly identical <a href="Pentium_III" title="Pentium III">Pentium III</a>, which only added the then-new <a href="Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> instruction set. However, the older family would continue to be produced until June 2001 for desktop units,<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> September 2001 for mobile units,<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> and the end of 2003 for embedded devices.<sup id="cite_ref-embdiscontinued_1-1" class="reference"><a href="#cite_note-embdiscontinued-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>

</p><p>Intel officially declared end-of-life and discontinued Pentium II processors on January 1, 2005.

</p>

<div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2></div>

<p>The Pentium II microprocessor was largely based upon the <a href="Microarchitecture" title="Microarchitecture">microarchitecture</a> of its predecessor, the <a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, but with some significant improvements.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>

</p><p>Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a <a href="Slot_1" title="Slot 1">slot</a>-based module rather than a <a href="CPU_socket" title="CPU socket">CPU socket</a>. The processor and associated components were carried on a <a href="Daughterboard" class="mw-redirect" title="Daughterboard">daughterboard</a> similar to a typical expansion board within a plastic cartridge. A fixed or removable <a href="Heatsink" class="mw-redirect" title="Heatsink">heatsink</a> was carried on one side, sometimes using its own fan.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>

</p><p>This larger package was a compromise allowing Intel to separate the secondary <a href="CPU_cache" title="CPU cache">cache</a> from the processor while still keeping it on a closely coupled <a href="Back-side_bus" title="Back-side bus">back-side bus</a>. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, its associativity was increased to 16-way (compared to 4-way on the Pentium Pro) and its size was always 512 KB, twice of the smallest option of 256 KB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level.<sup id="cite_ref-TomsPIIKlamath_7-0" class="reference"><a href="#cite_note-TomsPIIKlamath-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AnandP2klamath_8-0" class="reference"><a href="#cite_note-AnandP2klamath-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>

</p><p>Intel improved <a href="16-bit" class="mw-redirect" title="16-bit">16-bit</a> code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The issues with partial registers was also addressed by adding an internal flag to skip pipeline flushes whenever possible.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> To compensate for the slower L2 cache, the Pentium II featured 32 KB of L1 cache, double that of the Pentium Pro, as well as 4 write buffers (vs. 2 on the Pentium Pro); these can also be used by either pipeline, instead of each one being fixed to one pipeline.<sup id="cite_ref-PIIMANUAL_10-0" class="reference"><a href="#cite_note-PIIMANUAL-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> The Pentium II was also the first P6-based CPU to implement the <a href="MMX_(instruction_set)" title="MMX (instruction set)">Intel MMX</a> integer <a href="SIMD" class="mw-redirect" title="SIMD">SIMD</a> instruction set which had already been introduced on the <a href="Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a>.<sup id="cite_ref-TomsPIIKlamath_7-1" class="reference"><a href="#cite_note-TomsPIIKlamath-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>

</p><p>The Pentium II was a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as <a href="Windows_9x" title="Windows 9x">Windows 9x</a>, and multimedia applications. The slower and cheaper L2 cache's performance penalty was mitigated by the doubled L1 cache and architectural improvements for legacy code. General processor performance was increased while costs were cut.<sup id="cite_ref-TomsPIIKlamath_7-2" class="reference"><a href="#cite_note-TomsPIIKlamath-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup>

</p><p>All <i>Klamath</i> and some early <i>Deschutes</i> Pentium IIs use a combined L2 cache controller / <a href="Tag_RAM" class="mw-redirect" title="Tag RAM">tag RAM</a> chip that only allows for 512 MB to be cached; while more RAM could be installed in theory, this would result in very slow performance. While this limit was practically irrelevant for the average home user at the time, it was a concern for some workstation or server users. Presumably, Intel put this limitation deliberately in place to distinguish the Pentium II from the more upmarket Pentium Pro line, which has a full 4 GB cacheable area. The '82459AD' revision of the chip on some 333 MHz and all 350 MHz and faster Pentium IIs lifted this restriction and also offered a full 4 GB cacheable area.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="Variants">Variants</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Klamath">Klamath</h3></div>

<p>The original <i>Klamath</i> Pentium II microprocessor (Intel product code 80522) ran at 233, 266, and 300 <a href="Megahertz" class="mw-redirect" title="Megahertz">MHz</a> and was produced in a 0.35 <a href="Micrometre" title="Micrometre">μm</a> process.<sup id="cite_ref-TomsPIIKlamath_7-3" class="reference"><a href="#cite_note-TomsPIIKlamath-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-sandpileP2_15-0" class="reference"><a href="#cite_note-sandpileP2-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The 300 MHz version, however, only became available in large quantities later in 1997.<sup id="cite_ref-sandpileP2_15-1" class="reference"><a href="#cite_note-sandpileP2-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> These CPUs had a 66 MHz <a href="Front-side_bus" title="Front-side bus">front-side bus</a> and were initially used on motherboards equipped with the aging <a href="List_of_Intel_chipsets#Pentium_Pro/II/III_chipsets" title="List of Intel chipsets">Intel 440FX</a> <i>Natoma</i> chipset designed for the Pentium Pro.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> Pentium II-based systems using the <a href="List_of_Intel_chipsets" title="List of Intel chipsets">Intel 440LX</a> <i>Balboa</i> chipset widely popularized <a href="SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> (which was to replace <a href="Dynamic_random_access_memory" class="mw-redirect" title="Dynamic random access memory">EDO RAM</a> and was already introduced with 430VX), and the <a href="Accelerated_Graphics_Port" title="Accelerated Graphics Port">AGP</a> graphics bus.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>

</p><p>On July 14, 1997, Intel announced a version of the Pentium II <i>Klamath</i> with 2× 72-bit ECC L2 cache for entry-level servers, as opposed to the 2× 64-bit non-ECC L2 cache on regular models.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> The extra bits give it error-correction capability built into hardware, without impacting performance. The variant can be determined through the CPU part number.

</p><p>In Intel's "Family/Model/Stepping" scheme, Klamath CPUs are family 6, model 3.

</p>

<div class="mw-heading mw-heading3"><h3 id="Deschutes">Deschutes</h3></div>

<p>The <i>Deschutes</i> core Pentium II (80523), which debuted at 333 MHz in January 1998, was produced with a 0.25 <a href="Micrometre" title="Micrometre">μm</a> process and has a significantly lower power draw.<sup id="cite_ref-sandpileP2_15-2" class="reference"><a href="#cite_note-sandpileP2-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The die size is 113 mm<sup>2</sup>. The 333 MHz variant was the final Pentium II CPU that used the older 66 MT/s <a href="Front-side_bus" title="Front-side bus">front-side bus</a>; all subsequent Deschutes-core models used a 100 MT/s FSB. Later in 1998, Pentium IIs running at 266, 300, 350, 400, and 450 MHz were also released.<sup id="cite_ref-sandpileP2_15-3" class="reference"><a href="#cite_note-sandpileP2-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The <i>Deschutes</i> core introduced FXSAVE and FXRSTOR instructions for fast FPU context save and restore.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> Towards the end of its design life, Deschutes chips capable of 500 MHz within Intel cooling and design specifications were produced. However, these were not marketed. Rather than destroy already multiplier-locked units, those Deschutes units that had been tested and locked with a multiplier of 5 were sold as being 333 MHz. This was accomplished by disabling the 100 MHz bus option. <a href="Overclockers" class="mw-redirect" title="Overclockers">Overclockers</a>, upon learning of this, purchased the units in question and ran them well over 500 MHz; most notably, when overclocking, the final batch of "333 MHz" CPUs were capable of speeds much higher than CPUs sold at 350, 400, or 450 MHz.

</p><p>Concurrent with the release of Deschutes cores supporting a 100 MT/s front-side bus was Intel's release of the <a href="Intel_440BX" title="Intel 440BX">440BX</a> <i>Seattle</i> chipset and its derivatives, the 440MX, 450NX, and 440ZX chipsets. Replacing the aged 66 MHz FSB, which had been on the market since 1993, the 100 MHz FSB resulted in solid performance improvements for the Pentium II lineup. Pentium II chips starting with 350 MHz were released in both SECC and SECC2 form factors. Late Pentium IIs also marked the switch to <a href="Flip-chip" class="mw-redirect" title="Flip-chip">flip-chip</a> based packaging with direct heatsink contact to the die, as opposed to traditional bonding.

</p><p>While <i>Klamath</i> features 4 cache chips and simulates dual-porting through interleaving (2x 64-bit) for a slight performance improvement on concurrent accesses, <i>Deschutes</i> only sports 2 cache chips and offers slightly lower L2 cache performance at the same clockspeed. Furthermore, <i>Deschutes</i> always features ECC-enabled L2 cache.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup>

</p>

<p>The <a href="Pentium_II_Xeon" class="mw-redirect" title="Pentium II Xeon">Pentium II Xeon</a> was a high-end version of Deschutes core intended for use on <a href="Workstation" title="Workstation">workstations</a> and <a href="Server_(computing)" title="Server (computing)">servers</a>. Principally, it used a different type of slot (<a href="Slot_2" title="Slot 2">Slot 2</a>), case, board design, and more expensive full-speed custom L2 cache, which was off-die. Versions were produced with 512 KB, 1 MB or 2 MB L2 caches by varying the number of 512 KB chips incorporated on the board.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup>

</p>

<p>In Intel's "Family/Model/Stepping" scheme, Deschutes CPUs are family 6, model 5 and have the part number 80523.

</p>

<div class="mw-heading mw-heading4"><h4 id="Pentium_II_OverDrive">Pentium II OverDrive</h4></div>

<p>In 1998, the 0.25 μm Deschutes core was utilized in the creation of the <a href="Intel_Pentium_II_Overdrive" class="mw-redirect" title="Intel Pentium II Overdrive">Pentium II Overdrive</a> processor, which was aimed at allowing corporate <a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a> users to upgrade their aging servers. Combining the Deschutes core in a <a href="Flip-chip" class="mw-redirect" title="Flip-chip">flip-chip</a> package with a 512 KB full-speed L2 cache chip from the Pentium II Xeon into a <a href="Socket_8" title="Socket 8">Socket 8</a>-compatible module resulted in a 300 or 333 MHz processor that could run on a 60 or 66 MHz front-side bus. This combination brought together some of the more attractive aspects of the Pentium II and the Pentium II Xeon: <a href="MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> support/improved 16-bit performance and full-speed L2 cache, respectively.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> The later "Dixon" mobile Pentium II would emulate this combination with 256 KB of full-speed cache.

</p><p>In Intel's "Family/Model/Stepping" scheme, the Pentium II OverDrive CPU identifies itself as family 6, model 3, though this is misleading, as it is not based on the family 6/model 3 Klamath core. As mentioned in the Pentium II Processor update documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core."<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="Tonga">Tonga</h3></div>

<p>The 0.25 μm <i>Tonga</i> core was the first mobile Pentium II and had all of the features of the desktop models.

</p><p>In Intel's "Family/Model/Stepping" scheme, Tonga CPUs are family 6, model 5.

</p>

<div class="mw-heading mw-heading3"><h3 id="Dixon">Dixon</h3></div>

<p>Later, in 1999, the 0.25; 0.18 (400 <a href="Hertz" title="Hertz">MHz</a>) μm <i>Dixon</i> core with 256 KB of on-die full speed cache was produced for the mobile market. Reviews showed that the Dixon core was the fastest type of Pentium II produced.<sup id="cite_ref-sandpileP2_15-4" class="reference"><a href="#cite_note-sandpileP2-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup>

</p><p>In Intel's "Family/Model/Stepping" scheme, Dixon CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the <i>Mendocino</i> <a href="Mendocino_(microprocessor)" class="mw-redirect" title="Mendocino (microprocessor)">Celeron</a> processors.

</p>

<div class="mw-heading mw-heading2"><h2 id="Core_specifications">Core specifications</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Desktop">Desktop</h3></div>

<div class="mw-heading mw-heading4"><h4 id="Klamath_(80522)">Klamath (80522)</h4></div>

<ul><li>L1 cache: 16 + 16 KB (Data + Instructions)</li>

<li>L2 cache: 512 KB, as external chips on the CPU module clocked at half the CPU frequency.</li>

<li>Packaging: <a href="Slot_1" title="Slot 1">Slot 1</a> module</li>

<li><a href="Front-side_bus" title="Front-side bus">Front-side bus</a>: 66 MT/s, <a href="GTL%2B" class="mw-redirect" title="GTL+">GTL+</a></li>

<li>VCore: 2.8 V</li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a>: 350 nm CMOS</li>

<li>First release: May 7, 1997</li>

<li>Clockrate: 233, 266, 300 MHz</li></ul>

<div class="mw-heading mw-heading4"><h4 id="Deschutes_(80523)">Deschutes (80523)</h4></div>

<ul><li>L1 cache: 16 + 16 KB (Data + Instructions)</li>

<li>L2 cache: 512 KB, as external chips on the CPU module clocked at half the CPU frequency.</li>

<li>Packaging: <a href="Slot_1" title="Slot 1">Slot 1</a> module</li>

<li><a href="Front-side_bus" title="Front-side bus">Front-side bus</a>: 66, 100 MT/s, <a href="GTL%2B" class="mw-redirect" title="GTL+">GTL+</a></li>

<li>VCore: 2.0 V</li>

<li>Process: 250 nm CMOS</li>

<li>First release: January 26, 1998</li>

<li>Clockrate: 266–450 MHz

<div class="mw-heading mw-heading3"><h3 id="Deschutes_(Pentium_II_Overdrive)">Deschutes (Pentium II Overdrive)</h3></div>

<ul><li>L1 cache: 16 + 16 KB (Data + Instructions)</li>

<li>L2 cache: 512 KB external chip on CPU module running at 100% of CPU speed</li>

<li>Socket: <a href="Socket_8" title="Socket 8">Socket 8</a></li>

<li><a href="Front-side_bus" title="Front-side bus">Front-side bus</a>: 60 or 66 MT/s, <a href="GTL%2B" class="mw-redirect" title="GTL+">GTL+</a></li>

<li>VCore: 3.1–3.3 V (Has on-board voltage regulator)</li>

<li>Fabrication: 250 nm</li>

<li>Based on the <a href="#Deschutes">Deschutes</a>-generation Pentium II</li>

<li>First release: 1998</li>

<li>Supports <a href="MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> technology</li>

<li>The sSpec number SL2KE denotes a Pentium II Overdrive sold with an integrated heatsink/fan combination for Socket 8. [Note that the sSpec number SL2EA denotes a Pentium II Overdrive sold with an integrated heatsink but no fan for Slot 1.]</li></ul>

<div class="mw-heading mw-heading3"><h3 id="Mobile">Mobile</h3></div>

<div class="mw-heading mw-heading4"><h4 id="Tonga_(80523)">Tonga (80523)</h4></div>

<p><b>Mobile Pentium II</b>

</p>

<ul><li>L1 cache: 16 + 16 KB (Data + Instructions)</li>

<li>L2 cache: 512 KB, as external chips on the CPU module clocked at half the CPU frequency.</li>

<li>Package: <a href="MMC-1" title="MMC-1">MMC-1</a>, <a href="MMC-2" title="MMC-2">MMC-2</a>, <a href="Mini-Cartridge" title="Mini-Cartridge">Mini-Cartridge</a></li>

<li><a href="Front-side_bus" title="Front-side bus">Front-side bus</a>: 66 MT/s, <a href="GTL%2B" class="mw-redirect" title="GTL+">GTL+</a></li>

<li>VCore: 1.6 V</li>

<li>Process: 250 μm CMOS</li>

<li>First release: April 2, 1998</li>

<li>Clockrate: 233, 266, 300 MHz</li></ul>

<div class="mw-heading mw-heading4"><h4 id="Dixon_(80524)">Dixon (80524)</h4></div>

<p><b>Mobile Pentium II PE ("Performance Enhanced")</b>

</p>

<ul><li>L1 cache: 16 + 16 KB (Data + Instructions)</li>

<li>L2 cache: 256 KB, on-die, full speed.</li>

<li>Package: <a href="BGA1" class="mw-redirect" title="BGA1">BGA1</a>, <a href="MMC-1" title="MMC-1">MMC-1</a>, <a href="MMC-2" title="MMC-2">MMC-2</a>, <a href="Micro-PGA1" class="mw-redirect" title="Micro-PGA1">μPGA1</a> PPGA-B615</li>

<li><a href="Front-side_bus" title="Front-side bus">Front-side bus</a>: 66, 100 MT/s, <a href="GTL%2B" class="mw-redirect" title="GTL+">GTL+</a></li>

<li>VCore: 1.5, 1.55, 1.6, 2.0 V</li>

<li>Process: 250, 180 (400 <a href="Hertz" title="Hertz">MHz</a>)  nm CMOS</li>

<li>First release: January 25, 1999</li>

<li>Clockrate: 266, 300, 333, 366, 400 MHz</li>

<li>Containing 27.4 million <a href="Transistor" title="Transistor">transistors</a></li>

<li><a href="Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size (<a href="Semiconductor" title="Semiconductor">semiconductor</a> chip) is 10.36 mm x 17.36 mm = 179.85 mm<sup>2</sup></li></ul>

<ul><li><a href="List_of_Intel_Pentium_II_microprocessors" class="mw-redirect" title="List of Intel Pentium II microprocessors">List of Intel Pentium II microprocessors</a></li>

<li><a href="Intel_Celeron" class="mw-redirect" title="Intel Celeron">Intel Celeron</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://web.archive.org/web/*/http://www.heise.de/ct/english/98/18/020/">Wayback machine archive of Heise, accessed June 17, 2009</a></span>

</li>

<li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110831012432/http://download.intel.com/design/PentiumII/specupdt/24333749.pdf">"Intel Pentium II Processor Specification Update"</a> <span class="cs1-format">(PDF)</span>. July 2002. Archived from <a rel="nofollow" class="external text" href="http://download.intel.com/design/PentiumII/specupdt/24333749.pdf">the original</a> <span class="cs1-format">(PDF)</span> on August 31, 2011.</cite></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20050419074301/http://users.erols.com/chare/remark.htm">Listing of various PII, PIII, and Celeron alphanumeric model designations</a></li>

<li><a rel="nofollow" class="external text" href="http://www.cpu-info.com/index2.php?mainid=html/cpu/iP2.php">CPU-INFO: Intel Pentium II, indepth processor history</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210417105338/https://www.namebrightstatic.com/images/header_bg.png">Archived</a> April 17, 2021, at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li>

<li><a rel="nofollow" class="external text" href="http://smithsonianchips.si.edu/ice/cd/9706_542.pdf">Construction Analysis: Intel 266MHz 32-Bit Pentium II (Klamath) Processor</a>, Integrated Circuit Engineering Corporation</li></ul>

<p><b>Intel datasheets</b>

</p>

<ul><li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/Pentium%20II/24333503.PDF">Pentium II (Klamath)</a></li>

<li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/Pentium%20II/24365703.PDF">Pentium II (Deschutes)</a></li>

<li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/Pentium%20II/24366902.PDF">Mobile Pentium II (Tonga)</a></li>

<li><a rel="nofollow" class="external text" href="http://download.intel.com/design/mobile/datashts/24510301.pdf">Mobile Pentium II in Micro-PGA and BGA packages (Dixon)</a></li></ul>

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</style><div id="Intel_processors144" style="font-size:114%;margin:0 4em"><a href="List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="List_of_Intel_processors" title="List of Intel processors">Processors</a>

<li><a href="List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li>

<li><a href="List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a>

<li><a href="Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li>

<li><a href="List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li>

<li><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li>

<li><a href="List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li>

<li><a href="Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li>

<li><a href="NetBurst" title="NetBurst">NetBurst</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li>

<li><a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>

<ul><li><a href="Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li>

<li><a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>

<ul><li><a href="Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li>

<li><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>

<ul><li><a href="Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li>

<li><a href="Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>

<ul><li><a href="Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li>

<li><a href="Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a>

<ul><li><a href="Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li>

<li><a href="Willow_Cove" title="Willow Cove">Willow Cove</a></li>

<li><a href="Golden_Cove" title="Golden Cove">Golden Cove</a>

<ul><li><a href="Raptor_Cove" class="mw-redirect" title="Raptor Cove">Raptor Cove</a></li></ul></li>

<li>Redwood Cove</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86" title="X86">x86</a> <a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>

<ul><li><a href="Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li>

<li><a href="Silvermont" title="Silvermont">Silvermont</a></li></ul></li>

<li><a href="Goldmont" title="Goldmont">Goldmont</a>

<ul><li><a href="Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li>

<li><a href="Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>

<ul><li><a href="Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li>

<li>Crestmont</li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em">

<li><a href="Celeron" title="Celeron">Celeron</a></li>

<li><a href="Pentium" title="Pentium">Pentium</a></li>

<li><a href="Intel_Core#Core_and_Core_Ultra_3/5/7/9" title="Intel Core">Core Ultra</a>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="X86" title="X86">x86</a> (<a href="16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X87" title="X87">x87</a> (external <a href="Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<dl><dt>8/16-bit databus</dt>

<dt>16-bit databus</dt>

<dt>32-bit databus</dt>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="RapidCAD" title="RapidCAD">RapidCAD</a></li>

<li><a href="I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li>

<li><a href="Celeron" title="Celeron">Celeron</a> (1998)

<li><a href="Pentium" title="Pentium">Pentium</a>

<ul><li><a href="Pentium_(original)" title="Pentium (original)">Original i586</a></li>

<li><a href="Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li>

<ul><li><a href="List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li>

<li><a href="List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li>

<li><a href="List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li>

<li><a href="Intel_Quark" title="Intel Quark">Quark</a></li>

<li><a href="Tolapai" title="Tolapai">Tolapai</a></li></ul>

<li><a href="Celeron" title="Celeron">Celeron</a>

<li><a href="Pentium" title="Pentium">Pentium</a>

<li><a href="Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li>

<ul><li><a href="List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<dd><a href="Itanium" title="Itanium">Itanium</a></dd>

<dd><a href="StrongARM" title="StrongARM">StrongARM</a></dd>

<dd><a href="XScale" title="XScale">XScale</a></dd></dl>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li>

<li><a href="List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a>

<li><a href="Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li>

<li><a href="PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li>

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li>

<li><a href="Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-08-06" href="https://en.wikipedia.org/wiki/?title=Pentium_II&oldid=1304463799">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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